A pseudo-dual port memory has a first port, a second port, and an array of
six-transistor memory cells. A first memory access is initiated upon a
rising edge of a first clock signal received onto the first port. A
second memory access is initiated in response to a rising edge of a
second clock signal received onto the second port. If the rising edge of
the second clock signal occurs within a first period of time, then the
second memory access is initiated immediately following completion of the
first memory access in pseudo-dual port fashion. If the rising edge of
the second clock signal occurs later within a second period of time, then
the second memory access is delayed until after a second rising edge of
the first clock signal. The durations of the first and second memory
accesses do not depend on the duty cycles of the clock signals.