The gate dielectric layer of a thin film field effect transistor is formed as a multilayer layer system having at least one self assembling molecular monolayer (SAM) and a dielectric polymer layer made of an insulating polymer. With comparatively small layer thicknesses of 10 to 50 nanometers, the multilayer gate dielectric layer ensures low leakage currents and enables failsafe operation of the thin film field effect transistor at low supply voltages of less than 5 volts. The gate dielectric layer is robust toward voltages of up to approximately 20 volts and permits the use of a multiplicity of different materials for realizing an underlying electrode.