A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.

 
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< Electronic device with serial ATA interface and power-saving control method used in the device

> Apparatus having a transfer mode abnormality detecting function, storage controlling apparatus, and interface module for the storage controlling apparatus

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