The present disclosure relates generally to systems and methods for tuning power consumption and group delay in circuits such as radio frequency integrated circuits (RFICs). In one example, a system includes first and second gating blocks configured to reduce a first clock signal operating at a first clock rate to a second clock rate and a third clock rate, respectively. A first processing block coupled to the first gating block operates at the second clock rate. A second processing block is coupled to the first processing block and the second gating block, and operates at the third clock rate. The first processing block changes a flag state from a first state to a second state when transmitting a first data sample to the second processing block, and changes the flag state from the second state to the first state when transmitting a second data sample to the second processing block.