Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode overlying the second P-type region. P-type source and drain regions are ion implanted into the first N-type region, and N-type source and drain regions are ion implanted into the second P-type region. First silicide regions, spaced apart from the first gate electrode by a first distance, are formed contacting the P-type source and drain regions, and second silicide regions, spaced apart from the second gate electrode by a second distance less than the first distance, are formed contacting the N-type source and drain regions.