An automatic digital-circuit design apparatus receives a control target model written in a design description language, generates a control target model represented by a finite state machine model, stores the generated control target model, receives a control specification model written in a design description language, generates a control specification model represented by a finite state machine model, stores the generated control specification model, generates a control apparatus synthesis model by composing the generated control target model and the generated control specification model, computes controllable simulation relation, stores the computed controllable simulation relation, determines whether the control apparatus synthesis model is a model capable of providing the control, generates a permissible operation model, stores the generated permissible operation model, determines a control rule, generates a control apparatus model represented by a finite state machine, and converts the control apparatus model to a control apparatus model written in a design description language.