A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semiconductor storage medium through the second bus, the process including generation of a relative address corresponding to an absolute address based on the received absolute address and generation of an identification signal indicating the relative address. The memory controller comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address corresponding to the relative address.