Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and fault simulation algorithms. Those algorithms that are independent from each other can be executed non-sequentially (e.g., in parallel). Allocation of the various algorithm portions for execution among various processors can be based in part on a queue length associated with the processor. The queue length is adjustable based on many factors including data indicating the status of an execution maintained by the controlled processors. The faster processors can have their queue lengths increased. Multiple queue lengths can be maintained to allow for changes in allocation based on the granularity of tasks being performed by the controlling processor.