The integrated circuit according to the invention comprises a processor (603), a non-volatile memory (602) and an interface (605), where said interface (605) contains a first cache memory (601.1) and a second cache memory (601.2) and connects the processor (603) to the non-volatile memory (602). The interface (605) gets data from the non-volatile memory (602) and stores them in said first or said second cache memory (601.1, 601.2) intermediately and provides the processor (603) with data from said first cache memory (601.1) or from said second cache memory (601.2), depending on where the requested data are stored.