A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches include control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance depending on an electrical voltage that is applied across the resistive element, and wherein the second voltage level is between the plate voltage level and the first voltage level.