Techniques for optimizing application specific integrated circuit (ASIC)
and other IC pin assignment corresponding to a high density interconnect
(HDI) printed circuit board (PCB) layout are provided. Applying the
techniques described herein, pin assignments may be systematically and
strategically planned, for example, in an effort to reduce the PCB layer
count and associated cost, increase signal integrity and speed, reduce
the surface area used by an ASIC and its support circuitry, reduce plane
perforations, and reduce via crosstalk when compared to conventional
designs with an ASIC mounted on a multilayered PCB.