A GPS receiver depends on CMOS technology for both its GPS digital signal processing (DSP) and radio frequency (RF) stages. A resulting increase in RF input noise generated by the CMOS RF input is overcome by placing the antenna on-chip or on a lid of an application specific integrated circuit (ASIC) that includes the DSP and RF stages, and matching it for the best noise figure rather than the best impedance match. The on-chip antenna is matched to the natural high impedance of the CMOS RF input without requiring matching networks that can attenuate already weak signals. Using CMOS technology for both the GPS DSP and RF stages eliminates the need for level shifts between what would otherwise be a 3-volt RF section and a 1.2-volt DSP section.