A method and related apparatus for adjusting/calibrating timing of memory
signals. In a preferred embodiment of the invention, reference signals of
the same frequency and different phase are generated by a phase-lock
loop. These reference signals are used to trigger sampling of signals for
generating signals of different timing/delay; then timing/delay of memory
signals, such as clock, command, data and data strobe, can be adjusted
and calibrated. In this way, the invention can avoid the use of delay
lines while adjusting/calibrating memory signals, so as to reduce the
negative effects of characteristics shift and variation of delay lines.