A sequence detector (1600-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (1402-w), comparison circuitry (1603-w), and symbol generation circuitry (1604, 1605-w, and 1606) for converting digital values of an input signal into a sequence of symbols chosen from an alphabet of predefined symbols allocated into multiple non-overlapping families each formed with a plurality of the predefined symbols. The branch metric generator makes intra-family branch selections, each of which is one of a plurality of branches respectively corresponding to a family's symbols, and generates corresponding branch metrics. The comparison circuitry determines state metrics and generates corresponding comparison results. The symbol generation circuitry utilizes the comparison results and the branch selections, or selection information generated from the branch selections, to generate the sequence of predefined symbols.