A semiconductor package for surface mounting has a substrate having electrode patterns formed on both its surfaces which are electrically connected through passages such as throughholes formed through the substrate, all of these electrode patterns having a metal film formed by an electrolytic plating process. Semiconductor chips are wire-bonded onto one its surfaces (mounting surface) which is sealed with a resin layer. Lead-in wires each with one end exposed externally are included only those of the electrode patterns on the back surface of the substrate opposite its mounting surface such that the mounting surface has no lead-in wires with a part exposed externally.

 
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< Three-dimensional stack manufacture for integrated circuit devices and method of manufacture

> Method to fabricate interconnect structures

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