A multilayer printed wiring board (10) includes: a build-up layer (30) that is formed on a core substrate (20) and has a conductor pattern (32) disposed on an upper surface; a low elastic modulus layer (40) that is formed on the build-up layer (30); lands (52) that are disposed on an upper surface of the low elastic modulus layer (40) and connected via solder bumps (66) to a IC chip (70); and conductor posts (50) that pass through the low elastic modulus layer (40) and electrically connect lands (52) with conductor patterns (32). The conductor posts (50) have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 .mu.m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer (40), is greater than or equal to the aspect ratio Rasp of internal conductor posts (50b), which are positioned at internal portions of the low elastic modulus layer (40).