A three-dimensional flash memory array incorporates thin film transistors
having a charge storage dielectric arranged in series-connected NAND
strings to achieve a 4F.sup.2 memory cell layout. The memory array may be
programmed and erased using only tunneling currents, and no leakage paths
are formed through non-selected memory cells. Each NAND string includes
two block select devices for respectively coupling one end of the NAND
string to a global bit line, and the other end to a shared bias node.
Pairs of NAND strings within a block share the same global bit line. The
memory cells are preferably depletion mode SONOS devices, as are the
block select devices. The memory cells may be programmed to a near
depletion threshold voltage, and the block select devices are maintained
in a programmed state having a near depletion mode threshold voltage.
NAND strings on more than one layer may be connected to global bit lines
on a single layer. By interleaving the NAND strings on each memory level
and using two shared bias nodes per block, very little additional
overhead is required for the switch devices at each end of the NAND
strings. The NAND strings on different memory levels are preferably
connected together by way of vertical stacked vias, each preferably
connecting to more than one memory level. Each memory level may be
produced with less than three masks per level.