A prognostic processor for predicting machine failure in avionics electronics comprises prognostic capabilities in a single integrated circuit, with a processor, volatile and non-volatile memory, clock, on-chip and off-chip sensors and transducers, A/D converters, a common I/O interface adapted to be employed in a network of similar prognostic processors, and predictive Failure Analysis (FA) model software, which may be distributed throughout the network. The FA software employs a log file history, with the log file history storing data collected by the prognostic processor, real-time execution of a predictive model, with the ability to update the FA model with data from field failures. The prognostic processor network supports hierarchical processing to work with multiple prognostic processors. The prognostic processor system is applicable to FA monitoring of a wide range of avionics electronic equipment, in particular, Line Replacement Units (LRUs).