A method of operating a programmable logic device includes the steps of using a full V.sub.DD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 V.sub.DD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full V.sub.DD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced V.sub.DD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.