One embodiment of the present invention is a method for making metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening has sidewalls and bottom and a width of less than about 0.13 .mu.m, and the method includes: (a) depositing by a PVD technique a PVD seed layer over the substrate, said PVD seed layer being sufficiently thick over the field to enable uniform electroplating across the substrate; (b) depositing by a CVD technique a CVD seed layer over the PVD seed layer, wherein (i) the CVD seed layer having a thickness of less than about 150 .ANG. over the field, (ii) the CVD seed layer is continuous over the sidewalls and bottom surfaces, (iii) at least one of the seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, and (iv) the seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening; and (c) filling the at least one opening by electroplating a metallic layer over the CVD seed layer, wherein the electroplated metallic layer includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals.