A reduced storage capacitor is used for shrinking a memory cell in DRAM,
and local bit line is divided into short line for reducing parasitic
capacitance. For reading, a first reduced swing amplifier as a local
sense amp reads the memory cell through the local bit line, and a second
reduced swing amplifier as a global sense amp reads the local sense amp
through a global bit line. With the multi-stage sense amps, time domain
sensing scheme is realized such that a voltage difference in the local
bit line is converted to a time difference, for differentiating high data
and low data, and also fast read operation is realized. And write
operation is executed by a reduced swing write driver. With reduced
voltage swing, pseudo negative word line scheme is realized for retaining
data, and power consumption is reduced. In addition, various alternative
circuits and memory cell structures are implemented.