A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS, when activating a shallow source/drain extension region.