A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

 
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< Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

> System and method for providing content-addressable magnetoresistive random access memory cells

> Magneto-resistive element

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