High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

 
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< Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise

> Reducing power consumption during read operations in non-volatile storage

> Programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory

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