A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artifacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.