A system and method provides accurate time generation in a computing
device that includes a computing device clock and a microprocessor. The
method includes determining a total system latency based on a delay
incurred between issuance of a first command by the microprocessor and
receipt of a first time-data signal by the microprocessor. The first
time-data signal is representative of a master clock output of a master
clock device at a first time. The method also includes deriving an
accurate time from a second time-data signal. The second time-data signal
is representative of the master clock output at a second time known by
the microprocessor. The method further includes adjusting the accurate
time based on a percentage of the total system latency to form a latency
adjusted time, and applying the latency adjusted time to the computing
device clock to synchronize the computing device clock to the master
clock output.