Error-free data transfer between mesochronous clock domains can be
accomplished by writing data to and reading data from a plurality of data
storage elements in coordinated fashion. Write operations are controlled
by execution of a state sequence synchronously with the source clock
domain, and read operations are controlled by execution of the same state
sequence synchronously with the destination clock domain. The states
respectively correspond to the data storage elements, and the read and
write executions of the state sequence do not simultaneously assume the
same state.