Methods and apparatus provide for automated synthesis of an integrated circuit whose voltage is varied during operation (also known as dynamic voltage and frequency scaling or DVFS). The automation may include estimating technology parameters from timing libraries, and determining a translation factor that can be used in estimating path delays for an arbitrary voltage from path delays at another voltage. The automation may also include estimating a relative difficulty to synthesize a design for meeting sets of timing constraints specified at different operating voltages and frequencies by assigning one of the constraints a common base value among all the sets, translating the other constraint to maintain equivalency of synthesis difficulty, comparing the resulting equivalent constraints to identify a hardest-to-synthesis constraint set, and using that constraint set as a goal for a first synthesis of the circuit.