A flash memory device includes a storage area having a main memory portion
and a cache memory portion storing at least one bit per cell less than
the main memory portion; and a controller that manages data transfer
between the cache memory portion and the main memory portion according to
at least one caching command received from a host. The management of data
transfer, by the controller, includes transferring new data from the host
to the cache memory portion, copying the data from the cache memory
portion to the main memory portion and controlling (enabling/disabling)
the scheduling of cache cleaning operations.