A microelectronic topography includes a dielectric layer (DL) with a
surface higher than an adjacent bulk metal feature (BMF) and further
includes a barrier layer (BL) upon the BMF and extending higher than the
DL. Another microelectronic topography includes a BL with a metal-oxide
layer having a metal element concentration which is disproportionate
relative to concentrations of the element within metal alloy layers on
either side of the metal-oxide layer. A method includes forming a BL upon
a BMF such that portions of a first DL adjacent to the BMF are exposed,
selectively depositing a second DL upon the BL, cleaning the topography
thereafter, and blanket depositing a third DL upon the cleaned
topography. Another method includes polishing a microelectronic
topography such that a metallization layer is coplanar with a DL and
further includes spraying a deionized water based fluid upon the polished
topography to remove debris from the DL.