A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.

 
Web www.patentalert.com

< Pattern enhancement by crystallographic etching

< Semiconductor device with thin-film transistors and method of fabricating the same

> Electrophoretic display panel and method of fabricating the same

> Sensor, thin film transistor array panel, and display panel including the sensor

~ 00608