A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.
Web www.patentalert.com
< Multiple page size address translation incorporating page size prediction
< Multiple address sequence cache pre-fetching
> Cached field replaceable unit EEPROM data
> Method for booting a host device from an MMC/SD device, a host device bootable from an MMC/SD device and an MMC/SD device method a host device may booted from
HOME | NEW USER | LOGIN | SUBSCRIPTIONS | SEARCH | GUESTBOOK | CONTACT