A method, system, and computer program product are disclosed for optimizing logic during synthesis of a logic design. A first timing path within the logic design is identified. The first timing path has first logic to be optimized in order to improve timing in the first timing path. A determination is then made regarding whether an input node to the first timing path is a particular device. In response to the input node being the particular device, a determination is made regarding whether optimizing second logic included in a second timing path having the particular device as its output node will improve timing in the first timing path. In response to a determination that optimizing the second logic will improve timing in the first timing path, both the second logic and the first logic are selected to be optimized.