A semiconductor memory includes a silicon substrate having a cell array
region wherein plural rectangular silicon pillars are formed in rows and
columns by a trench having a width of 1a and formed in a lattice form, a
storage node formed on at least a surface of a lower portion of the
silicon pillar, a well region formed in an upper half above the storage
node, a diffusion layer formed on an upper surface of the well region, a
capacitor dielectric formed on the storage node to surround the lower
portion of the silicon pillar, a plate electrode buried in the lower
portion of the trench to substantially the same level as the upper end of
the storage node, and a first gate electrode formed on the channel portion
via a first gate insulator.
