A method for using timing simulation and authentication software of an EDA tool
(electronics design automatic tool) to bypass a plurality of clock trees in the
EDA tool. The EDA tool contains a plurality of clocking devices that prevent the
timing simulation and authentication software from changing an order of the plurality
of clocking devices. The method includes measuring a delay time of the clocking
device, and providing a first buffer, which is electrically connected to the clocking
device, according to the delay time, wherein the delay time of the first buffer
approximates the delay time of the clocking device.
