A test circuit for testing a first memory including a plurality of memory cells
includes a first address decoder couplable to the first memory, the first address
decoder configured for receiving a first input address and generating a first signal
in response thereto for selectively accessing one or more of the memory cells in
the first memory. The test circuit further includes a second memory including a
plurality of memory cells and a second address decoder couplable to the second
memory, the second address decoder configured for receiving a second input address
and generating a second signal in response thereto for selectively accessing one
or more of the memory cells in the second memory array. A sense circuit operatively
couplable to the first and second memory arrays is configured to substantially
simultaneously read data from at least one memory cell in the first memory and
data from at least one corresponding memory cell in the second memory, the data
in the at least one memory cell in the first memory being complementary to the
data in the at least one corresponding memory cell in the second memory array.
The at least one corresponding memory cell in the second memory has a controllable
output drive associated therewith.
