In designing a semiconductor device, a method of verifying an upper-hierarchy
logic including a lower-hierarchy logic. First, a first verification logic having
an output terminal, which is equivalent to an input terminal of the lower-hierarchy
logic, and an input terminal, which is equivalent to an output terminal of the
lower-hierarchy logic. Then, a second verification logic including only the input
terminal and output terminal of the lower-hierarchy logic is produced, and an operational
verification of the upper-hierarchy logic is executed using the first and second
verification logics. This method eliminates the need for performing an operational
verification of the lower-hierarchy logic at the time of the operational verification
of the upper-hierarchy logic.
