A transistor (10) is formed as a matrix of transistor cells (13)
that have drain metal strips (50) for contacting drains (15) of the
transistor cells and source metal strips (55) for contacting sources (35)
of the transistor cells. An interconnect layer (1030) overlying the matrix
of transistor cells has first portions (201) that contact one the drain
metal strips with first and second vias (79) and second portions (101)
that contact one of the source metal strips with third and fourth vias (78).
