For use in a processor having a first number of decode units for decoding an
ordered stream of floating point instructions, a floating point unit (FPU) for
receiving decoded ones of the floating point instructions and a method of processing
the decoded ones of the floating point instructions. In one embodiment, the FPU
includes: (1) a second number of floating point pipelines that execute the floating
point instructions, the second number being at least one and less than the first
number, the floating point pipeline having a load unit, an execution core and a
store unit, (2) a floating point checkpoint buffer, coupled to the decode units,
that queues the decoded ones of the floating point instructions for allocation
to the floating point pipelines and (3) a floating point register file, coupled
to and cooperable with the floating point checkpoint buffer, that preserves states
of the execution core to allow the floating point pipelines to execute the floating
point instructions out of order.
