A gate electrode 14 is formed through a gate oxide film 13 over
a
channel region 12 in an element region 11, and sidewall dielectric
films 16 are provided on side sections of the gate electrode 14.
Source/drain regions 17 include low concentration impurity regions 171
and high concentration impurity regions 172. The impurity regions 172
are provided, by an over-etching method when forming the sidewalls 16,
at a disposition level LV2 in the element region 11, which is lower
than a disposition level LV1 where the impurity regions 171 are disposed.
Assisting impurity regions 173 are provided in regions where the levels
change between level LV1 and LV2. As a result, the continuity of
impurity regions between the impurity regions 172 and the impurity regions
171 that are low concentration extension regions is secured, the their electrical
connection is stabilized.
