A method for manufacturing a MOS transistor integrated into a chip of semi-conductive
material comprising a first and a second active region which extend from the inside
of the chip to a surface of the chip. The method comprises the steps of: a) forming
a layer of insulating material on the surface of the chip and depositing a layer
of conductive material on said insulating layer, b) defining an insulated gate
electrode of the transistor, from said superimposed insulating and conductive layers,
c) defining, from said superimposed insulating and conductive layers, an additional
structure arranged on a first surface portion of the first active region, and d)
placing between the insulated gate electrode and the additional structure a dielectric
spacer placed on a second surface portion of the first active region.
