A high-performance, superscalar-based computer system with out-of-order instruction
execution for enhanced resource utilization and performance throughput. The computer
system fetches a plurality of fixed length instructions with a specified, sequential
program order (in-order). The computer system includes an instruction execution
unit including a register file, a plurality of functional units, and an instruction
control unit for examining the instructions and scheduling the instructions for
out-of-order execution by the functional units. The register file includes a set
of temporary data registers that are utilized by the instruction execution control
unit to receive data results generated by the functional units. The data results
of each executed instruction are stored in the temporary data registers until all
prior instructions have been executed, thereby retiring the executed instruction in-order.
