Memory storage device with segmented column line array

   
   

A memory storage device includes a first and second memory cell which each have a top end and a bottom end. A first and second first dimension conductor are substantially coplanar and parallel and extend in a first dimension. The first first dimension conductor intersects the bottom end of the first memory cell and the second first dimension conductor intersects the top end of the second memory cell. A first second dimension conductor extends in a second dimension and intersects the top end of the first memory cell and a second second dimension conductor extends in the second dimension and intersects the bottom end of the second memory cell. A first third dimension conductor which extends in a third dimension is positioned between the first and second memory cell to couple the first second dimension conductor to the second second dimension conductor.

 
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