Each of N memory blocks of first to Nth stages includes a plurality
of first and second driver units. The plurality of first and second driver units
are respectively provided corresponding to one end and another end of a plurality
of digit lines included in each memory block. Each of the first driver units in
memory blocks before a selected memory block connects a corresponding digit line
to a first voltage according to a voltage level on a digit line of the same row
in a memory block of a previous stage. A second driver unit in the selected memory
block connects a corresponding digit line to a second voltage in order to supply
a data write current. In other words, digit lines in the memory blocks before the
selected memory block are not used as current lines but as signal lines.
