Some embodiments of the invention provide a method of identifying routes in
a region of an integrated circuit ("IC") design layout. The region contains at
least one net with several routable elements. The method decomposes the IC design-layout
region into a tessellated graph. The tessellated graph includes a plurality of
edges. The method then specifies a route that connects the net's routable elements
by specifying a set of edges that the route intersects.