Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit ("IC") design layout. The method receives a set of nets. Each net in the set has a set of routable elements in the IC design-layout region. For each net, the method then specifies a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes.

 
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