The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.