A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.

 
Web www.patentalert.com

< System and method suitable for receiving gigabit ethernet signals

< Stacked high-voltage ESD protection clamp with triggering voltage circuit control

> Analog signal interface for digital control

> Pipelined analog-to-digital converter (ADC) with 3-bit ADC and endpoint correction
~ 00238