Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating a portion of a layout to form space tiles, which are used to interpret a flow graph. The flow graph comprises a set of vertices and edges. The capacity of edges in the flow graph is used to identify the maximum flow for that portion of the layout. In another approach, an edge walk is performed against a set of space tiles, in which a nearest neighbor determination is determined for each edge to perform maximum flow analysis.

 
Web www.patentalert.com

< Semiconductor device and method for fabricating the same

< Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs

> Method and apparatus for determining viability of path expansions

> High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation

~ 00281