A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

 
Web www.patentalert.com

< Compositions and methods for high-efficiency cleaning/polishing of semiconductor wafers

< Method of manufacturing semiconductor apparatus

> Quad flat non-leaded package comprising a semiconductor device

> Semiconductor device and method for manufacturing the same

~ 00294